Modeling Microprocessor Performance

Name: Modeling Microprocessor Performance
Brand: Springer-Verlag New York Inc.
SKU: 9781461375432
Price: 105.32 EUR
Availability: InStock

Автор: Bibiche Geuskens, Kenneth Rose

Език:

Корици: С меки корици

Издател: Springer-Verlag New York Inc.

Наличност: Външен склад

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Modeling Microprocessor Performance focuses on the development of a design and evaluation tool, name...

Информация за книгата

Автор

Bibiche Geuskens, Kenneth Rose

Език

Английски език

Корици

Книга - С меки корици

Издадена

2012

страници

195

EAN

9781461375432

ISBN

1461375436

Enbook ID

06796963

Издател

Springer-Verlag New York Inc.

Теглоt

338

Размери

155 x 235 x 12

Пълно описание

Modeling Microprocessor Performance focuses on the development of a design and evaluation tool, named RIPE (Rensselaer Interconnect Performance Estimator). This tool analyzes the impact on wireability, clock frequency, power dissipation, and the reliability of single chip CMOS microprocessors as a function of interconnect, device, circuit, design and architectural parameters. It can accurately predict the overall performance of existing microprocessor systems. For the three major microprocessor architectures, DEC, PowerPC and Intel, the results have shown agreement within 10% on key parameters. §The models cover a broad range of issues that relate to the implementation and performance of single chip CMOS microprocessors. The book contains a detailed discussion of the various models and the underlying assumptions based on actual design practices. As such, RIPE and its models provide an insightful tool into single chip microprocessor design and its performance aspects. At the same time, it provides design and process engineers with the capability to model, evaluate, compare and optimize single chip microprocessor systems using advanced technology and design techniques at an early design stage without costly and time consuming implementation. §RIPE and its models demonstrate the factors which must be considered when estimating tradeoffs in device and interconnect technology and architecture design on microprocessor performance.

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