Verilog by Example

Name: Verilog by Example
Brand: Full ARC Press
SKU: 9780983497301
Price: 20.67 EUR
Availability: InStock

A Concise Introduction for FPGA Design

Автор: Blaine Readler

Език:

Корици: С меки корици

Издател: Full ARC Press

Наличност: Външен склад

Изпращаме след 9-15 дни

20.67 € 40.43 лв

A practical primer for the student and practicing engineer already familiar with the basics of digit...

Информация за книгата

Автор

Blaine Readler

Език

Английски език

Корици

Книга - С меки корици

Издадена

2011

страници

124

EAN

9780983497301

ISBN

9780983497301

Enbook ID

07434756

Издател

Full ARC Press

Теглоt

202

Размери

154 x 227 x 8

Пълно описание

A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.

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